1. Field of the Invention
This invention relates to a semiconductor device. More particularly, the invention relates to an electrostatic discharge (ESD) protection device.
2. Description of Related Art
Progress in semiconductor technology has decreased the dimensions of many semiconductor devices. As very large scale integration (VLSI) circuit geometry continues to shrink, the corresponding gate oxide thickness has also continued to decrease. This decrease in thickness, relative to breakdown voltage, has resulted in an increased susceptibility to damage from the application of excessive voltages. For example, an electrostatic discharge (ESD) event is capable of developing such an excess voltage. During an ESD event, charge is transferred between one or more pins of the device and another conducting object in a time period that is typically less than one microsecond. This charge transfer can develop voltages that are large enough to break down insulating films (e.g., gate oxides) on the device, or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.
Accordingly, ESD protection and its impact on the reliability of IC products in submicron CMOS technologies has become a primary concern. The resulting protection circuits may typically be connected to all Input/Output (I/O) pads of an integrated circuit (IC) to safely dissipate the energy associated with ESD events without causing any damage to the circuitry internal to the device. Protection circuits have also been connected to power supply pads, or between power supply buses to prevent such damage to internal circuits.
An ESD protection circuit that includes a silicon controlled rectifier (SCR) is considered to have very good electrostatic discharge performance. Since the SCR ESD protection circuit has a low snap-back holding voltage of about 1 to 5 volts and a low effective resistance of about 1 to 3 Ohms, it provides a very good discharge condition for the electrostatic current.
However, the breakdown voltage of the SCR ESD protection circuit is still too large. Therefore, it is possible that the SCR ESD protection circuit is not triggered when an ESD even occurs. This will damage the internal circuit. In addition, the current process is a kind of ultra shallow junction, and the junction area is too small to provide an effective trigger current. Furthermore, a larger layout area is required.
Therefore, there are needs to develop a new SCR structure that the breakdown voltage can be reduced and adjusted on demands. Furthermore, the SCR structure can also provide a smaller layout area.